This invention relates generally to programmable devices such as field programmable gate arrays, and specifically to methods for booting up a microcontroller without losing port connections to a host computer.
FIG. 1 shows a conventional Field Programmable Gate Array (FPGA) 1 having an array of configurable logic blocks (CLBs) 2 surrounded by input/output blocks (IOBs) 3. The CLBs 2 are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure 4 includes a matrix of programmable switches (PSMs) 5 which can be programmed to selectively route signals between the various CLBs 2 and IOBs 3 and thus produce more complex functions of many input signals. The IOBs 3 can be configured to drive output signals from the CLBs 2 to external pins (not shown) of FPGA 1 and/or to receive input signals from the external FPGA pins.
The CLBs 2, IOBs 3, and PSMs 5 of FPGA 1 are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs 2, IOBs 3, and PSMs 5. These memory cells control various switches and multiplexers within respective CLBs 2, IOBs 3, and PSMs 5 which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA 1 via a configuration port 6 and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. No. Re34,363, U.S. Pat. Nos. 5,430,687, 5,742,531, and 5,844,829). Configuration port 6 is connected to the dedicated configuration structure by a configuration access port (CAP) 7, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in xe2x80x9cThe Programmable Logic Data Book 1998xe2x80x9d, published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG. 2. Well known design tool software operating on a suitable microprocessor within host system 20 creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system 20 to interface cable 15 using, for instance, a serial port or a USB port. The interface cable 15 preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system 20 into a format usable by target FPGA 10, although in some embodiments host system 20""s microprocessor is used to customize the configuration bitstream for target FPGA 10. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
In some embodiments, the interface cable is connected to the host system over the USB port, which allows for greater data flow than an RS-232 serial port. Well known USB standards require peripheral devices attached to the USB port of a host system to identify themselves within a predetermined time after being detected by the host system. Specifically, according to the USB Specification, Revision 1.0, a host computer with a USB port uses two data lines, each having pull-down resistors attached with resistances of 15 kxcexa9xc2x15%. These are weak pull-down resistors and assure that the two data lines will have logic 0 levels when there is no device attached to the USB port of the host computer. A peripheral device attached to this USB port must have a pull-up resistor with resistance of 1.5 kxcexa9xc2x15% attached to one of the two data lines. Thus, when a device is attached to the USB port, the host computer will detect a high voltage on one line (the low-resistance pull-up resistor in the peripheral device will override the host""s pull-down resistor). The host detects a xe2x80x9cconnectxe2x80x9d condition when one of the data lines is pulled high for more than 2.5 xcexcs. In response to this combination of high and low voltages, the host expects a sequence of identifying signals from the peripheral device. If no such signals are forthcoming, the host disconnects from the peripheral device and the peripheral device is thereafter not able to communicate with the host. Thus, if the interface cable""s on-board FPGA and microcontroller cannot boot up and identify the interface cable to the host system within the predetermined time period, the host system closes the USB port, thereby undesirably preventing communication with the interface cable.
The present invention provides a method for disguising a device""s connection to a USB port of, for instance, a host system such as a personal computer or workstation.
In accordance with the present invention, an FPGA interface device having a microcontroller is connected to a host system using a USB port connection. A switch is coupled between one of the data pins of the USB port and a supply voltage. When the interface device is connected to the host system via the USB port, the switch is turned off so as not to pull a USB data pin to the supply voltage, and thereby prevents the host system from detecting the presence of the interface device on the USB port. The switch is maintained in a non-conductive state until the microcontroller on the interface device is booted up and has retrieved identification codes for the interface device. When ready, the microcontroller turns the switch on, thus allowing detection by the host of a peripheral device attached to its USB port. In this manner, the host system is delayed in detecting the connection of the interface device to the host system""s USB port until the interface device is ready to provide suitable identification codes to the host system.